The present invention relates to a scheduling circuit and more particularly to a scheduling circuit applicable to an ATM (Asynchronous Transfer Mode) communication network.
Scheduling circuits for the above application are disclosed in, e.g., Japanese Patent Laid-Open Publication No. 11-340983 and a paper 2 “B-8-12”, The Institute of Electronics, Information and Communication Engineers of Japan, 1999 General Meeting.
In a transmission network in which IP (Internet Protocol) is mapped and a communication terminal included therein, suitable delay is added at the output side of the apparatus on an IP packet or an ATM cell basis in accordance with traffic rates, which are dependent on notified values. The delay frees the network and a receiving terminal connected to the above terminal from excessive loads. In this case, a sequence of processing for smoothing the traffic, i.e., scheduling is essential for controlling data to be sent.
A conventional scheduling circuit includes an IP scheduling section, a format converting section, and an ATM scheduling section. The problem with such a conventional scheduling circuit is that both the IP scheduling section and ATM scheduling section discard a datagram. As a result, a datagram is discarded excessively, depending on the traffic.